1. Technical Field of the Invention
This invention relates to digital processing for quick signal processing in an adder circuit while the adder circuit is rounding, and more particularly, the present invention is a circuit for detecting zero in an adder system and using this to provide convergent rounding.
2. Description of Related Art
A Multiply and Accumulator (MAC) device contains the logic structures required to perform arithmetic operations on data. A MAC may comprise a fractional multiplier, an arithmetic logic unit (ALU), a shifter, and accumulators. An ALU is typically comprised of at least a Booth decoder for converting the ALU inputs into parallel bytes for internal processing, a Wallace tree for controlling multiplexing and shifting, and an Adder.
On the bit level, a simple adder is an organization of logic circuits, typically comprising one Exclusive OR (XOR) gate and one AND gate. The simple adder (adder) numerically adds two binary bits together to produce a two-bit binary output which is typically divided into a sum bit and a carry bit. When adding more than two one-bit numbers, additional logic structures are necessary.
Because the basic logic gate of a single adder stage is a two-input XOR gate, the most basic adding device, the adder, adds only two bits at a time. In order to add larger numbers together, several single adder stages must be placed in parallel and the logic must be enhanced to account for carry bits. Likewise, before reporting the results of an adding operation, the adder must first account for all of the values carried from less significant bits all the way through the adder. This add and carry, add and carry, add and carry process takes considerable time (called a propagation delay). Many attempts have been made to speed up the add operation.
In Realization of Transmission-Gate Conditional-Sum (TGCS) Adders with Low Latency Time by Rothermel, et. al, the authors advocate using TGCS adders because of the adders"" short propagation delay and similarities to complementary metal oxide semiconductor (CMOS) circuits. Realization of Transmission-Gate Conditional-Sum (TGCS) Adders with Low Latency Time, T. Rothermel, et. al, IEEE Journal of Solid State Circuits, Vol. 24, No. 3, June 1989, p. 558.
In Evaluation of A+B=K Conditions Without Carry Propagation, Cortadella and Liaberia propose a method and design for evaluating A+B=K conditions without using carry propagation. Evaluation of A+B=K Conditions Without Carry Propagation, J. Cortadella and J. Liaberia, IEEE Transactions on Computers, Vol. 41, No. 11, November 1992 p. 1484. This is the method of circuit design commonly used today to compare the result of an add operation to a predetermined number.
In the situation where an adder must perform a rounding operation, the time delay can become very significant. This is caused when rounding operations require logic zeros be detected for some of the simple adders that make up the adder block of the ALU. Thus, a check must be made for the presence of zeros after the completion of an add operation. This operation is usually performed by an AND operation which provides additional time delays to the ALU operations. Since the zero detection must be performed for each cycle of the ALU, the time delays are cumulative.
Therefore, it is advantageous to have an adder circuit for detecting zeros in order to accelerate the time required for the rounding operation.
In accordance with the present invention, there is provided an adder circuit that comprises a summing circuit to provide a summed sliced bit number from a first sliced bit number and a second sliced bit number. A boundary circuit is operably connected to the summing circuit to form a rounding boundary between selected groups of the summed sliced bit number. A rounding circuit is operably connected to the boundary circuit to detect a zero in each slice of the summed sliced bit number while the first and second sliced bit numbers are being added to one another. The rounding circuit includes a logic circuit to detect the zero and provide a zero detect output and a control circuit to selectively round the summed sliced bit number up and down in response to the zero detect output.
Further, in accordance with the present invention, there is provided a method of improving the speed of an adder. The method comprises the steps of slicing first and second bit numbers into first and second sliced bit numbers. A rounding boundary is formed between selected groups of the first and second sliced bit numbers. The first and second sliced bit numbers are added to form a summed sliced bit number. A zero is detected at each slice of the summed slice bit number. A zero detect output is provided in response to each detected zero. Each summed sliced bit number is then selectively rounded up and down in response to the zero detect output.
Further, in accordance with the present invention, there is provided a multiply and accumulator circuit. The multiply accumulate circuit comprises first and second registers to store a first operand A and a second operand B. A decoder is operably connected to said first and second registers to create a partial product from each of the first and second operands A and B. A partial product summation tree circuit is operably connected to the decoder circuit to create a first bit number A and a second bit number B and to partially add bit numbers A and B to one another. An adder circuit for adding bit numbers A and B to one another to produce a summed bit number C is operably connected to the partial product summation tree. The adder circuit includes a summing circuit to provide a summed sliced bit number from a first sliced bit number and a second sliced bit number. A boundary circuit is operably connected to the summing circuit to form a rounding boundary between selected groups of the summed sliced bit number. A rounding circuit is operably connected to the boundary circuit to detect a zero in each slice of the summed sliced bit number while the first and second sliced bit numbers are being added to one another. The rounding circuit includes a logic circuit to detect the zero and provide a zero detect output and a control circuit selectively rounds the summed sliced bit number up and down in response to the zero detect output.